1. Field of the Invention
The present invention relates to a semiconductor device including an interconnection, which has an interconnection main layer containing Cu (copper) as the main component (i.e., by 50% or more), wherein such an interconnection will be also referred to as a Cu interconnection, for the sake of convenience. The present invention also relates to a semiconductor device manufacturing method for forming such an interconnection by a barrier self-formation process. Particularly, the present invention relates to a semiconductor device and manufacturing method thereof, utilizing a damascene interconnection structure.
2. Description of the Related Art
In recent years, interconnection structures employing Cu and an insulating film with a low dielectric constant have been developed to increase the speed and integration degree of silicon (Si) semiconductor integrated circuits. Where a Cu interconnection structure is used for an integrated circuit, the Cu interconnection easily causes counter diffusion relative to an insulating layer around it, or easily causes a reaction in an oxygen atmosphere and produces a Cu oxide film, during various heat treatments used for manufacturing the integrated circuit. In order to prevent these problems, it is necessary to form a diffusion barrier film, such as a tantalum (Ta) or tantalum nitride (TaN) film, before the Cu layer (interconnection main layer) is formed. Particularly, where an embedded Cu layer is formed in an interlevel insulating film, as in a damascene interconnection structure, Cu diffusion into the insulating film becomes prominent, and thus a diffusion barrier film is indispensable.
In order to ensure that Cu interconnection structures are reliable, they need to have a barrier film with a thickness of 10 nm or more, under the present process technique. However, barrier films are required to be thinner with generation changes to reduce the interconnection resistance, because the interconnection width will decrease, thereby increasing the resistance. In this respect, conventional barrier film formation methods entail some difficulties in depositing a barrier film on the side surface of an interconnection groove or via-hole (interconnection hole) with uniform thickness and quality. As a consequence, it is difficult to ensure a required barrier property level of the barrier film, the adhesiveness at the interface between the barrier film and Cu layer, and the resistance against electro migration due to interface diffusion, thereby causing problems in reliability.
As an ultimate arrangement to solve these problems while reducing the thickness of the barrier film, a barrier-less structure, which does not include any conventional barrier film formation process, is conceivable. It has been proposed, as a method of forming a barrier-less structure, to add an alloy element in a Cu layer and perform a heat treatment on the Cu layer, so as to diffuse the alloy element to the interface between the Cu layer and an insulating layer, at which the alloy element reacts with the insulating layer and thereby forms a stable compound.
Major elements reported so far to be usable as the alloy element described above are Al, Mg, and Sn. However, these elements greatly increase the electric resistance, while there is no report saying that they form a stable compound at the interface. Accordingly, under the present circumstances, a barrier-less structure is expected as an ultimate interconnection structure, but is considered to be very difficult to achieve. In this respect, although a barrier-less structure was included in loadstars for the future on the roadmap of ITRS (International Technology Roadmap for Semiconductor) in 1999, it was excluded therefrom in 2001.
As described above, conventionally, where an interconnection structure employs a Cu interconnection formed in an interlevel insulating film, a barrier film is required to ensure the reliability of the structure. However, the presence of the barrier film brings about problems, such as an increase in interconnection resistance, and a decrease in interconnection reliability. On the other hand, although a barrier-less structure is expected as an ultimate interconnection structure, such a structure is very difficult to achieve. Accordingly, it is desired to provide a semiconductor device and manufacturing method thereof which can improve the reliability of an interconnection structure and decrease the interconnection resistance.
The following publications disclose techniques relating to the present invention:
[Patent publication 1]
Jpn. Pat. Appin. KOKAI Publication No. 2-62035
[Non-patent publication 1]
W. A. Lanford et al., Thin Solid Films, 262 (1995) 234-241